1. Field of the Invention
The present invention relates to a semiconductor wafer, a semiconductor chip and a method for manufacturing of the semiconductor device and the semiconductor wafer.
2. Related Art
Dicing process and etching process have conventionally been employed as methods for dividing a plurality of semiconductor devices formed on a wafer into individual devices. Such kind of technique is disclosed in Japanese Patent Laid-Open No. 2002-93,752. In the method disclosed in Japanese Patent Laid-Open No. 2002-93,752, a surface of a wafer formed circuit is first adhered onto a tape component. A back surface of the wafer is ground while maintaining such condition, thereby thinning the wafer. Then, resist layers are formed in regions corresponding to the individual semiconductor devices on the ground back surface, and an etching is performed from the side of the back surface to divide the wafer into individual semiconductor devices. It is described that the available regions for being employed as semiconductor elements in the wafer can be increased by employing this process. It is also described that cracks on the wafer generated during the back grinding can be removed to provide the process for improving the reliability after the packaging.
On the other hand, a configuration having a plurality of LSIs on a wafer, which are mutually connected with interconnects, is disclosed in Japanese Patent Laid-Open No. S62-171,137 (1987). It is described that a plurality of LSIs can be simultaneously inspected by having the configuration comprising the interconnects formed between the LSIs.